An Asynchronous Add-Compare-Select Design in CMOS VLSI

机译：CMOS VLSI中的异步加比较选择设计

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A novel asynchronous ACS(Add-Compare-Select) is described. The circuit of a novel asynchronous comparator unit is proposed. The performance of ACS is analyzed with the novel method based on multi-delay model. The results of performance analysis of asynchronous ACS show that the average case response time 3.66ns is only 45% the worst-case response time 8.1ns. It reveals that the asynchronous ACS has some performance advantages than the synchronous one.

机译：描述了一种新颖的异步ACS（Add-Compare-Select）。提出了一种新型的异步比较器单元的电路。利用基于多延迟模型的新方法分析了ACS的性能。异步ACS的性能分析结果表明，平均情况响应时间3.66ns仅是最坏情况响应时间8.1ns的45％。结果表明，异步ACS比同步ACS具有一些性能优势。

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来源
《International Conference on ASIC; 20031021-20031024; Beijng; CN》|2003年|P.1277-1280|共4页
会议地点 BeijngCN
作者
Zhao Bing; Hei Yong; Qiu Yulin;
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作者单位

Microelectronics RD Centre Chinese Academy of Sciences Beijing, 100029, P.R.China;

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原文格式 PDF
正文语种 eng
中图分类计算技术、计算机技术;
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An Asynchronous Add-Compare-Select Design in CMOS VLSI

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