A 250M Hz clock for SOC systems

摘要

This paper introduces a method to implement a phase-locked loop (PLL) based on ring oscillator. In order to reject the jitters, a voltage regular is applied to reduce the power-supply noise, which is the most common and dominant source of jitter. The simulation result shows that the voltage regulator can achieve a power-supply rejection ratio (PSRR) greater than 50dB while VCO operating at frequencies about 1 GHz. And it is in layout. The system will be integrated in a 0.25-um 2-poly 5-metal digital CMOS technology.