Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures Based on Xilinx Virtex-II FPGAs

摘要

Due to the high performance and parallelism of FPGAs, this technology is now more and more common in the design and integration of system-on-chips, rather than exploited only for rapid prototyping purposes. With the new possibility of dynamical and partial reconfiguration, the performance and flexibility of an embedded system can be even further increased. Using this feature, functionality on the FPGA can be replaced on-demand during run-time. However, the design of dynamical and partial reconfigurable systems is very complicated and time-consuming. The designer must be careful since the misplacement of one signal line can lead to destruction of the FPGA during reconfiguration. In order to simplify the design process and improve the security, new methods and tools must be developed in order to perform the design process on a higher abstraction level. This paper describes the current design flow and its complications and presents new techniques to provide a high-abstraction level design flow, using the Embedded Development Tools Kit from Xilinx. The goal is to build up a library of application- and communication components for dynamical and partial reconfigurable systems for integration in the Embedded Development Tools Kit.