An all-digital phase-locked loop with a multi-delay-switching TDC

摘要

This paper presents a low-power time-to-digital converter (TDC) with multi-delay-switching mechanism for ADPLL application. In order to achieve low power dissipation and low area occupation, a switching mechanism is proposed on TDC design. The proposed ADPLL achieves the frequency range from 150 MHz to 1.45 GHz and 18.4 ps peak-to-peak jitter at 800 MHz. The design has been implemented in 0.18 um CMOS process with an active area of 0.1088 mm and the whole system consumes 8.41 mW at 800 MHz.