Retargetable Timed Instruction Set Simulation of Pipelined Processor Architectures

摘要

This paper presents a retargetable timed instruction set simulator for programmable architectures. The simulator is automatically generated from a machine description in the language LISA and its generic processor model. Based on the LISA machine descriptions, pipeline hazards of the processor model can be specified and analyzed to fulfill the specific requirements of processor design. The development of the new retargetable simulator was necessary since existing approaches are based on processor models which are either too inaccurate or cannot deliver acceptable simulation speed. The first part presents the generic machine model of the retargetable simulator. In the second part, the description of the TI TMS320C6201 signal processor and the generated simulator is discussed.