Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator

摘要

In the advent of System-on-Chip (SoC) technology, validation scope is further expanded from a single core to the system. Modules are also substituted by application specific instruction-set processors (ASIP) in order to raise abstraction level of systems from signals to instructions. As embedded processors are diversified according to their specific application, they suffer from an increasing number of irregular constraints and architectural idiosyncrasies. They also have control paths of pipeline which shows quite complicated timing. In order to alleviate these design complexities, validation must take retargetability and cycle-accuracy into consideration. We have thus proposed efficient embedded processor validation environment (EPVE) using a cycle-accurate retargetable instruction-set simulator (CARISS) as a reference model. The designed CARISS is based on an architecture description language (ADL), which provides improved retargetability for instruction-set machines. It also uses a scheduling method which can capture complex processor behavior more accurately than the ones used by the previous ADLs. We have applied the proposed EPVE for the 32bit embedded processors and investigated effectiveness of our approach by analyzing statistics on detected errors.