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Implementation of Digital Filters on Pipelined Processor with Multiple Accumulators and Internal Datapaths

机译:在具有多个累加器和内部数据路径的流水线处理器上实现数字滤波器

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This paper presents a set of techniques to automatically find rate optimal or near rate optimal implementations of shift-invariant flow graphs on pipelined processor, in which pipeline processor has multiple accumulators and internal datapaths. In such case, the problem to be addressed is the scheduling of multiple instruction streams which control all of the pipeline stages. The goal of an automatic scheduler in this context is to rearrange the order of instructions such that they are executed with minimum iteration period between successive iteration of defining flow graphs. The scheduling algorithm described in this paper also focuses on the problem of removing the hazards due to inter-instructiondependencies.
机译:本文提出了一套在流水线处理器上自动查找速率不变流图的速率最佳或接近速率最佳实现的技术,其中管线处理器具有多个累加器和内部数据路径。在这种情况下,要解决的问题是控制所有流水线级的多个指令流的调度。在这种情况下,自动调度程序的目标是重新排列指令的顺序,以使它们在定义流程图的连续迭代之间以最小的迭代周期执行。本文中描述的调度算法还着眼于消除因指令间依赖性而导致的危险的问题。

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