FPGA-based Design of Resource-Efficient Digital Down Converter

摘要

Digital down converter (DDC) is based on the theory of Software Defined Radio (SDR) and multirate signal processing, extensively applied in digital receivers of communications systems. An improved resource-efficient DDC with polyphase architecture and distributed arithmetic (DA) is presented in this paper. The design based on Xilinx FPGA Virtex-5 has more flexible characters and higher precision computation with less resource consumption.