Design and Optimization of an ARM Cortex-M Based SoC for TCP/IP Communication in High Temperature Applications

摘要

TCP/IP protocol stacks are usually complex protocols which require a high amount of computational power for the benefit of reliable communication. Therefore, a powerful and energy demanding processing core with an operating system is needed to achieve high data rates. In communication systems that are placed in a high temperature environment, e.g. electronics close to car engines or in aerospace applications, installation space is limited, temperatures of up to 175 ℃ occur and a high energy consumption leads to further self-heating. Thus, a robust high temperature ASIC is mandatory in order to provide an energy efficient and small processing platform. Special forms of the TCP/IP stack like Lightweight IP (lwIP) or Micro IP (uIP) are built for small or even embedded processors without the need of an operating system. In this work we implemented the lwIP and uIP stacks on the ARM Cortex-MO and ARM Cortex-M3 processors and measured the throughput of the resulting System on Chips (SoC) designed for high temperature applications. The results show a relatively poor throughput of maximum 20.29 MBit/s even for the more powerful Cortex-M3 processor using the lwIP stack. Software and hardware improvements like a Direct Memory Access (DMA) mechanism and extended checksum hardware could increase the performance by 1250% resulting in 228 MBit/s. As an exemplary target application, powerline communication in high temperature environment is chosen and a Design Space Exploration (DSE) was performed on the available physical parameters of a 180 nm SOI technology, capable of operating at 175 ℃. Results show that the best performing processor-software-combination is the Cortex-MO which has a size of only 0.374 mm2 and a power consumption of less than 1 mW at 10 MBit/s targeted throughput for the powerline application running the uIP stack. The increase in silicon area is only 9.7% and still this SoC is 2.57 times smaller and has 18.1 times less energy consumption compared to the Cortex-M3 baseline implementation.