A universal digital VLSI design for neural networks

摘要

Summary form only given. A universal digital VLSI design isnproposed for implementing a wide variety of artificial neural networks.nA programmable systolic array is presented based on a unified iterativenneural network model, which maximizes the strength of VLSI in terms ofnintensive and pipelined computing and yet circumvents the limitation onncommunication. The array is meant for a universal simulation tool andnneurocomputer architecture which can implement a variety of algorithmsnin both the retrieving and the learning phases of ANNs, e.g.nsingle-layer feedback networks, competitive learning networks,nmultilayer feedforward networks, and stochastic neural networks. Anfault-tolerance approach and partitioning scheme for large ornnonhomogeneous networks are also proposed