Empirical Interconnect Crosstalk Characterization for High Level Synthesis

摘要

As device geometries continue to get smaller delay and fault specification for deep-submicron technologies is evolving into a quite complicated task. The cumulative effect of gate delays are now less important than the interconnect delays, particularly in chip level interconnections. Potential crosstalk effects must also be taken into account. In this paper we concentrate on the crosstalk effects between neighboring wires in deep submicron interconnection structures and its characterization for use in higher levels of the design hierarchy. Realistic models were used and HSPICE simulation results are presented. Empirical generalization between experimental data and estimated crosstalk potential is performed.