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Coupled Circuit-Interconnect Modeling and Simulation

机译:耦合电路互连建模与仿真

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摘要

In this paper we discuss generating low order models for efficient coupled circuit-interconnect simulation. The ever increasing speeds and shrinking feature sizes that are typical of state of the art integrated circuits designs havem ade coupling due to interconnect and packaging a very important, sometimes dominant, factor in system performance. The ability to efficiently perform coupled circuit-interconnect simulation before fabrication is essential in order to detect signal degradation due to delays or crosstalk. We first discuss methods of generating models for both two and three dimensional interconnect and then present a general, guaranteed-stable, model order reduction technique to reduce the order of the interconnect models.
机译:在本文中,我们讨论了生成低阶模型以进行有效的电路互连仿真。随着互连和封装的发展,典型的最先进的集成电路设计不断增长的速度和缩小的特征尺寸具有耦合,这是系统性能中非常重要的,有时是主要的因素。为了检测由于延迟或串扰引起的信号劣化,在制造之前有效执行耦合电路互连仿真的能力至关重要。我们首先讨论为二维和三维互连生成模型的方法,然后介绍一种通用的,保证稳定的模型降阶技术,以减少互连模型的阶数。

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