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Design of a K-band fast hopping frequency synthesizer

机译:K波段快速跳频频率合成器的设计

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The design and implementation of a K-band fast hopping frequency synthesizer based on DDS and PLL is described. Main technical specifications are as follows: frequency ranges from 24GHz to 27GHz, step frequency is 50MHz and lock time is less than 150ns. The parameters of loop filter and the analyses of phase noise and lock time are provided by MATLAB simulation to verify the feasibility of the design. Final test results of the circuits proves that the targets of performance are achieved.
机译:描述了一种基于DDS和PLL的K波段快速跳频频率合成器的设计与实现。主要技术规格如下:频率范围为24GHz至27GHz,步进频率为50MHz,锁定时间小于150ns。 MATLAB仿真提供了环路滤波器的参数,并对相位噪声和锁定时间进行了分析,以验证设计的可行性。电路的最终测试结果证明可以达到性能目标。

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