Design of A 0.8GHz-3GHz Duty-Cycle Corrector With a 20-80 Input Duty Cycle

摘要

An analog duty cycle correction circuit using a novel pulsewidth modification cell. We correct the duty-cycle by changing the phase of the voltage. Our calibration allows the input duty cycle to range from 20% to 80%, and the circuit corrects the duty cycle to 50%. The proposed circuit operation frequency is at 0.8GHz to 3GHz, and it correctes to less than 1% error. The duty-cycle correction circuit is implemented in a 1.8V, and 180nm CMOS technology at 25°C.