Cost Effective Adaptive Voltage Scaling Using Path Delay Fault Testing

摘要

Application of manufacturing testing during the production process of integrated circuits is considered essential to ensure the quality of the devices used in the field. However, it is desirable to use the information gathered during the test process to add value to other aspects of the manufacturing process. This paper proposes a method to use path delay (PDLY) test patterns, not only to validate the functionality of the devices, but also as an alternative solution for performance estimation, that can be used for offline adaptive voltage scaling. This approach has many advantages over the currently used industrial performance estimation methods, so-called performance monitoring boxes (PMBs). Using simulation of ISCAS'99 benchmarks with 28nm FD-SOI libraries, the paper shows that the PDLY based approach reduces the inaccuracy of performance prediction from 2.32% (achieved by the classic PMB approach) to 1.85%, without the need for any on-chip monitors.