In the past 10 years, CMOS technology scaling has continued at the rate of every 1 陆 to 2 years per node. As CMOS technology advanced in to nano technology regime, static power or standby power increases at a much faster rate than dynamic power or active power, and it is expected to dominate the total device power dissipation. In this paper, we will review major leakage components that contributed to the significant rises in standby power and show the relationship between gate leakage and VCO performance. The results clearly show that the projected leakage at the 45nm node for advanced transistors will result in VCO performance that will not meet the stringent requirements for 3G solutions and beyond unless additional noise reduction techniques are utilized.
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