Generating Interlocked Instruction Pipelines from Specifications of Instruction Sets

摘要

The development of application specific processors (ASIPs) for systems-on-a-chip (SoCs) became increasingly popular in recent years. To efficiently develop such processors, respective tools are crucial. This paper presents methods to generate pipelined processors from a bare instruction set specification in ViDL . All microarchitectural aspects of the processor are contributed by a generator. Hazard resolution by forwarding, interlocking and branch prediction is automatically derived from instruction semantics, information on the targeted chip technology and an user supplied timing constraint. By variation of the latter, a set of compatible processor implementations is generated with different physical and dynamic characteristics. The processor generator has been evaluated using realistic instruction sets, such as ARM, MIPS, Power, SRC, DNACore and CoreVA. The generated processors have been tested on register-transfer-level and gate-level. In total, 83 processors have been generated and synthesized for a 65 nm STM low power technology, yielding clock frequencies of 260 - 680 MHz for 2 - 7 stage pipelines. Clock frequency and the number of cycles per instruction (CPI) is similar to handcrafted designs.