Measurements of gate lag in high quality nearly lattice matched InAlN/AlN/GaN HFET structures

摘要

The promise of InAlN-based HFET devices stems from the relatively large band and spontaneous polarization discontinuities and at the interface and the lack of misfit strain when grown lattice matched to GaN. However, there still exists some question as to what the true lattice matching condition of InAlN to GaN is due to discrepancies in the literature values of lattice parameters of the InN binary, and of the InAlN bowing parameters. We used the gate lag measurement as a supplementary technique to verify lattice matching to the underlying GaN, as we expect the strain in layers one source of lag, associated with piezoelectric charge at the surface. We observe very low lag for nearly lattice matched barrier and barriers under tensile strain, and a marked increase as the composition deviates from the lattice matched condition toward compressively strained layers. Additionally, FETs fabricated on a nearly lattice matched InAIN layer boasted a maximum drain current of over 1.5A/mm and ～2.0A/mm and transconductances of ～275mS/mm and ～300mS/mm at DC and in pulsed modes, respectively, and a cutoff frequency of 15.9GHz (an f_T~*L_G product of 10.3) for a gate length of 0.65μm.