Numerical Simulation and Optimization for 900V 4H-SiC DiMOSFET fabrication

摘要

We report the simulation results of 25 μm half cell pitch vertical type 4H-SiC DiMOSFET using the general-purpose device simulator MINIMOS-NT. The best trade-off between breakdown voltage and on-resistance in terms of BFOM is around 19MW/cm~2 with a p-well spacing 5 μm. The specific on -resistance, R_(ON, sp), simulated with V_(GS)=10V and V_(DS)=1V at room temperature, is around 22.76mΩcm~2. An 900V breakdown voltage is simulated with ion-implanted edge termination.