DRAM Controller with a Close-Page Predictor

摘要

Better insight of programs behavior can help in overcoming large speed difference of central processors and main memories implemented with DRAM chips. It allows us to predict required next actions, based on observed main memory access patterns, which can hide some time components in accessing DRAM memory. Authors of this paper proposed in [1] a simple dead time predictor which helps in predicting when to close the opened DRAM row. In this paper this predictor is further improved by adding a zero live time predictor. The zero live time predictor, by its essence, completes the dead time predictor from [1].