Systems and methods for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers that incorporate data maintenance blocks juxtaposed with memory modules or subsystems.

摘要

PROBLEM TO BE SOLVED: To provide a system and a method for holding dynamic random access memory (DRAM) data when reprogramming a reconfigurable device using a DRAM memory controller such as a field programmable gate array (FPGA). A DRAM memory controller is used in conjunction with a data maintenance block that is juxtaposed with a DRAM memory 102 and coupled to an I2C interface of a reconfigurable logic device. FPGAs drive most DRAM inputs / outputs (I / O). The data maintenance block drives the self-refresh command input. The data maintenance block provides a stable input level for self-refresh command inputs, even if the FPGA is reconfigured and most DRAM inputs are tri-state. [Selection diagram] Fig. 1