A NOVEL APPROACH TO CONTACT INTEGRATION AT 90-NM AND BEYOND

摘要

A contact integration, with low defect density, for 90-nm CMOS technology node is demonstrated. Patterning was achieved using 193nm lithography with a novel approach. Unique etch processes were developed to achieve sub-100nm contact CD and vertical sidewall. Defect improvement for this novel integration is presented. Improvements in electrical leakage performance are presented for this integration. Measurements of contact-to-poly-Si gate capacitance reveal dramatic reduction with shrunk contact CD achieved in this integration.