In modern day, embedded memory density and area on-chip is increasing, it is essential to define new test algorithms which fulfill the need of detecting new faults. The existing March algorithms consist of as many as four or seven operations per March element. In this paper we have presented an optimization of architecture which can implement these new March BLC tests having number of operations per element according to the today's growing needs of embedded memory testing with enhanced fault using Verilog HDL as a primary language and used Modelsim SE 6.5 f as simulation tool.
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机译：当今，嵌入式存储器的密度和片上面积不断增加，定义满足检测新故障需求的新测试算法至关重要。现有的March算法每个March元素最多包含四到七个运算。在本文中，我们提出了一种体系结构的优化方案，该方案可以实现这些新的March BLC测试，从而根据当今日益增长的对嵌入式内存测试的需求（使用Verilog HDL作为主要语言并使用Modelsim SE 6.5 f）来实现每个元素具有多个操作的功能。作为模拟工具。
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