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Optically interconnected integrated circuits to solve the CMOS interconnect bottleneck

机译:光互连集成电路解决了CMOS互连瓶颈

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The performance of future generation data processing systems will be set by interconnect limitations rather than by IC performance. The main reason for this expected I/O-bottleneck is the projected increase in CMOS IC-complexity, in terms of chip size, number of I/O pads and clock frequency. Problems inherently associated with closely packed electrical interconnections (such as cross-talk, signal distortion EMI) will lead to bandwidth limitations, in turn resulting in a mismatch between silicon processing capabilities and interconnect performance. Optical I/O over the entire chip area is pursued as a solution to these interconnection problems in the European Community funded ESPRIT project OIIC ("Optically Interconnected Integrated Circuits"). In this approach, data transfer from the whole chip area is facilitated through two dimensional arrays (array pitch: 250 /spl mu/m) of optical channels, consisting of opto-electronic components flip-chip mounted on CMOS circuitry and aligned to passive optical pathways. Data rate objectives are 0.5-1 Gb/s per channel. As a principal choice in this project, a 2D array of small diameter (125 /spl mu/m) Plastic Optical Fibres is used as a flexible transmission medium. The large numerical aperture of this fibre (typically NA=0.5) and its flexibility allow for compact assembly (and hence low head room modules) and relatively coarse alignment.
机译:下一代数据处理系统的性能将由互连限制而不是IC性能来决定。造成这种I / O瓶颈的主要原因是,预计在芯片尺寸,I / O焊盘数和时钟频率方面,CMOS IC复杂性将增加。与紧密封装的电气互连(例如串扰,信号失真EMI)固有相关的问题将导致带宽限制,进而导致硅处理能力和互连性能之间不匹配。在欧洲共同体资助的ESPRIT项目OIIC(“光互连集成电路”)中,在整个芯片区域上追求光I / O作为解决这些互连问题的方法。通过这种方法,可通过二维光通道阵列(阵列间距:250 / spl mu / m)来促进从整个芯片区域进行数据传输,该二维通道由倒装芯片安装在CMOS电路上并对准无源光学器件的光电组件组成途径。数据速率目标为每个通道0.5-1 Gb / s。作为该项目的主要选择,使用小直径(125 / spl mu / m)塑料光纤的2D阵列作为柔性传输介质。这种光纤的大数值孔径(通常为NA = 0.5)及其柔韧性可实现紧凑的组装(因此,低净空模块)和相对较粗的排列。

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