JPEG image compression hardware implementation with extensions for fixed-rate and compressed-image editing a

摘要

Abstract: This paper describes a new high speed image compression hardware implementation which, in addition to implementing the JPEG baseline system, can be used in fixed-rate compression systems and in systems that allow editing of compressed images. High speed (CCIR 601 resolution at 30 frames/second) and small silicon size are achieved by using a unique parameterized orthogonal transform. This implementation is compatible with the DCT, yet requires no additional multiplications. Also described here is a system that uses a dynamic quantization scalar circuit to achieve fixed-rate compression and a system that utilizes the `static coefficient DPCM' feature to compress and decompress regions of interest within an image for editing or viewing.!9