Low-power architecture for A 6-bit 1.6GS/s flash A/D converter

摘要

A 6-bit, 1.6-GS/s, flash ADC with a low-power architecture is presented. The proposed low-power architecture based on an analog input pre-processing method reduces the total number of comparators to almost two-thirds of that required in a conventional 6-bit, flash ADC. The advantages of the analog input pre-processing method include the low power consumption and small area due to the reduced number of comparators. The proposed flash ADC consumes 240 mW at a supply voltage of 1.8 V when implemented in a 0.18-mum CMOS technology. The simulated SNDR is 32 dB at an input frequency of 200 MHz.