NO FLOW UNDERFILL PROCESS DEVELOPMENT FOR FINE PITCH FLIP CHIP SILICON TO SILICON WAFER LEVEL INTEGRATION

摘要

The industry has witnessed the adoption of flip chip for itsrnlow cost, small form factor, high performance and great I/Ornflexibility. As the Three Dimensional (3D) packagingrntechnology moves to the forefront, the flip chip to waferrnintegration, which is also a silicon to silicon assembly, isrngaining more and more popularity.rnNo flow underfill is of a special interest for the wafer levelrnflip chip assembly as it can dramatically reduce the processrntime as well as bring down the average package cost sincernthere is a reduction in the number of process steps and therndispenser and cure oven that would be necessary for thernstandard capillary underfill process.rnThis paper introduces the development of no flow underfillrnprocess for a sub-100 micron pitch flip chip to CSP waferrnlevel assembly. Challenges addressed include the no flowrnunderfill reflow profile study, underfill dispense amountrnstudy, chip floating control and the underfill voidingrnanalysis. Also different no flow underfill candidates arerninvestigated for the best performed processing material.