Underfill Design for Low-K Dielectrics Lead Free Applications

摘要

As technology nodes progress to 32/28nm and beyondrnunderfill materials are presented with the significantlyrnchallenging task of maintaining bump protection whilernensuring ultra low-K dielectric (ULK/ELK) integrity.rnThis challenge is further complicated by the trend towardrnRoHS compliancy (lead-free) and an ever increasing diernsize. Through extensive research and testing, severalrnspecifically formulated underfill materials wererndetermined acceptable solutions for these complex issues.rnAs technology nodes progress to smaller processrngenerations a high stress concentration is seen at therndielectric layer during thermal cycling. This stress is arntypical result of a high glass transition temperature (Tg) /rnhigh strength material that often leads to a crackingrnfailure mode of the thin dielectric layer. Too low of a Tgrnpresents a high stress concentration on the bumps whichrnonce again constitutes failure, this time, however, therncrack is typically seen at the bump location. This highrnstress concentration seen at the bumps is more significantrnwhen lead free bumps are considered due to their inherentrnfragile nature. Underfill materials must now bernspecifically formulated and optimized to solve thesernfailure modes for a large variation of package types. Thisrnpaper will discuss solutions to typical failure modesrncurrently seen in reliability testing of present and futurerntechnologies. Keywords: flip chip, underfill, low-K dielectric, leadrnfree.