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Stacking of Known Good Rebuilt Wafers without TSV Applications to memories and SiP

机译：在不将TSV应用到存储器和SiP的情况下堆叠已知的良好重建晶圆

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来源
《Device packaging 2010》|2010年|p.1-7|共7页
会议地点 Scottsdale/Fountain Hills AZ(US)
作者
Christian Val; Pascal Couderc; Pierre Lartigues;
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作者单位

3D PLUSrn641, Rue Hélène Boucherrn78532 BUC – FrancernTel. + 33 1 30 83 26 50 –rnemail : cval@3d-Plus.com;

3D PLUSrn641, Rue Hélène Boucherrn78532 BUC – France;

3D PLUSrn641, Rue Hélène Boucherrn78532 BUC – France;

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原文格式 PDF
正文语种 eng
中图分类制造工艺;
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1. A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application [J] . Ko C.-T. Device and Materials Reliability, IEEE Transactions on . 2012,第2期

机译：基于微凸点/胶粘混合键合的Cu TSV晶圆级三维集成方案在三维存储中的应用
2. Study of Three-Dimensional Small Chip Stacking Using Low Cost Wafer-Level Micro-bump/B-Stage Adhesive Film Hybrid Bonding and Via-Last TSVs [J] . Yao Mingjun, Zhao Ning, Wang Teng, Journal of Electronic Materials . 2018,第12期

机译：使用低成本晶片级微凸块/ B级粘合膜混合粘接及通过最后TSV研究三维小芯片堆叠的研究
3. Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology [J] . D. Diehl, H. Kitada, N. Maeda, Microelectronic Engineering . 2012,第Apra期

机译：TSV的形成，用于利用无触点晶圆对晶圆技术堆叠高级逻辑器件
4. Stacking of Known Good Rebuilt Wafers without TSV Applications to memories and SiP [C] . Christian Val, Pascal Couderc, Pierre Lartigues IMAPS international conference and exhibition on device packaging . 2010

机译：堆叠已知的良好重建晶片，没有TSV应用到记忆和SIP
5. Power distribution in TSV based 3-D processor-memory stacks. [D] . Satheesh, Suhas M. 2012

机译：基于TSV的3D处理器内存堆栈中的功率分配。
6. Electronic Structure and Charge-Trapping Characteristics of the Al2O3-TiAlO-SiO2 Gate Stack for Nonvolatile Memory Applications [O] . Wenchao Xu, Yang Zhang, Zhenjie Tang, 2017

机译：非易失性存储应用中Al2O3-TiAlO-SiO2栅堆叠的电子结构和电荷俘获特性
7. Yield Improvement for 3D Wafer-to-Wafer Stacked Memories [O] . Mottaqiallah Taouil, Said Hamdioui 2012

机译：3D晶圆对晶圆堆叠式存储器的良率提高
8. Manufacturable Tri-Stack AlSb/InAs HEMT Low-Noise Amplifiers Using Wafer-Level-Packaging Technology for Light-Weight and Ultralow-Power Applications [R] . Chou, Y. C., Chang-Chien, P., Yang, J. M., 2009

机译：可制造的三叠层alsb / Inas HEmT低噪声放大器，采用晶圆级封装技术，适用于轻量级和超低功耗应用

Stacking of Known Good Rebuilt Wafers without TSV Applications to memories and SiP

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