A Process/Device/Design framework called the Parametric Yield Simulator is proposed for predicting circuit variability based on circuit design and a set of characterized sources of variation. In this simulator, the aerial image of a layout is simulated across a predefined process window and resulting non-idealities in geometrical features are communicated through to circuit simulators, where circuit robustness and yield can be evaluate in terms of leakage and delay variability. The purpose of this simulator is to identify problem areas in a layout and quantify them in terms of delay and leakage in a manner in which designers and process engineers can collaborate together on an optimal solution to the problem. The Parametric Yield Simulator will serve as a launch pad for collaborative efforts between groups in different disciplines that are looking at variability and yield. Universities such as Berkeley offer a great advantage in exploring innovative approaches as different centers of key expertise exist under one roof. For example a complementary set of characterization and validation experiments has also been designed and in a collaborative study is being executed at Cypress semiconductor on a 65nm NMOS process flow. This unique opportunity of having access to a cutting edge process flow with relatively high transparency has led to a new set of experiments with contributions from six different students in circuit design, process engineering, and device physics. Collaborative efforts with the device group have also led to a new electrical linewidth metrology methodology using enhanced transistors that could prove useful for process characterization.
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