FastYield: Variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization

摘要

While technology scaling has presented many new and exciting opportunities, new design challenges have arisen due to increased density, and delay and power variations. High-level synthesis has been touted as a solution to these problems, as it can significantly reduce the number of man hours required for a design by raising the level of abstraction. In this paper, we propose a new variation-aware high-level synthesis binding/module selection algorithm, named FastYield, which takes into consideration multiplexers, functional units, registers, and interconnects. Additionally, FastYield connects with the lower levels of the design hierarchy through its inclusion of a timing driven floorplanner guided by a statistical static timing analysis (SSTA) engine which is used to modify/enhance the synthesis solution. FastYield is able to incorporate spatial correlations of process variations in its optimization, which are shown to affect performance yield. On average, FastYield achieves a clock period that is 14.5% smaller, and a performance yield gain of 78.9%, when compared to a variation-unaware algorithm. By making use of accurate timing information, FastYield's rebinding improves performance yield by an average of 9.8% over the initial binding, for the same clock period. To the best of our knowledge, this is the first high-level synthesis binding/module selection algorithm that is layout-driven and variation aware.