We have investigated the surface quality of thick 10#mu#m Silicon-On-Insulator (SOI) wafers by comparing CMOS device performance and reliability of SOI wafers with those of bulk wafers. Large scale CMOS circuits, microcontrollers with 12Kbyte ROM and 512byte EEPROM, were fabricated on thick SOI wafers and on bulk wafers, and device performance and reliability were evaluated by means of functional tests and acceleration tests. A significant difference was observed onlyin the ROM bit-map failure analysis in the functional tests, in which the number of single bit failures (defined as a chain of up to 4 adjacent bit failures) was more evident on ROM fabricated on the thick SOI than that fabricated on bulk wafers. The result indicates that the crystal defects introduced by the initial oxygen concentration and excess film stress of the SiO_2 interlayer may cause signle bit failures. The SOI wafers were prepared by Direct Wafer Bonding (DWB) and a mechanical polishing technique to form a 10#mu#m active silicon layer and a 625#mu#m silicon substrate, which sandwiches a 0.25 #mu#m SiO_2 interlayer. Thick SOI wafers such as these are becoming a promising material for one-chip integration of CMOS devices and Micro Electrical Mechanical System (MEMS) devices.
展开▼
