Design and implementation of window delay-line ADC for low-power DC-DC SMPS

摘要

A window delay-line analog-to-digital converter (ADC) with programmable resolutions for digitally-controlled switch-mode power supplies (SMPS) used in low-power portable applications is proposed in this paper. Due to its simple, low-power architecture and small silicon area, this ADC can be fully integrated with a digital controller. The proposed ADC quantizes the output converter voltage within a window of the reference voltage. The ADC has been fabricated in a TSMC 0.18µm CMOS technology and verified as a part of a 976.56 KHz, 3.6 to 1.2 V buck DC-DC converter.