CMOS receiver circuits for high-speed data transmission according to LVDS-standard

摘要

For high speed data transmission between different integrated circuits on one circuit board several aspects have to be considered: to avoid reflections a termination at the receiver is needed; to reduce power consumption a low signal swing is required; to make the transmission insensitive to interferences differential signals have to be used. All of this is taken into consideration by using the 'IEEE-Standard for Low Voltage Differential Signals (LVDS)'. In one part of this standard the specifications for the receiver are given. To fulfill these requirements special amplifier circuits are necessary. They must be able to operate with a very small differential signal at the input (400 mV max.) and a strongly varying operating point (between 0 and 2.4 V). With a supply voltage of 2.5 V two complementary input stages are necessary. Their output signals have to be combined and amplified to full signal swing. Different circuits which fulfill these conditions are presented and compared based on transistor level simulation. To improve the timing behaviour and to increase the signal slope and the opening in the eye diagram the transistor dimensions of the circuits have been optimized by using the optimization tool OPSIM. For the two most promising circuits with a data rate of 1.0 respectively 1.4 GBit/s and a power consumption of approximately 1 respectively 4 mW a full custom layout was created by using a modul generator environment and a design assistant. These two circuits have been realized in a 0.25 μm CMOS technology. Measurement results of the two circuits are presented.