Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)

机译：芯片多处理器（CMP）可行的片上互连网络的设计

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In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-mutti processor (CMP). It adopts a wormhole switching technique and its routing algorithm is livelock-/deadlock- free in 2D-me

机译：在本文中，提出了一种用于柔性片上互连网络的自适应虫洞路由器，并将其用于片上多处理器（CMP）。它采用虫洞切换技术，其路由算法在2D-me中无活锁/无死锁

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《Computer Architecture and High Performance Computing (SBAC-PAD), 2007 19th International Symposium on》|2007年|P.211-218|共8页
会议地点 GramadoRio Grande do SulBrazil
作者
Seung Eun Lee; Jun Ho Bahn; Bagherzadeh; N.;
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multiprocessor interconnection networks; system-on-chip; 2D mesh topology; adaptive router architecture; adaptive routing algorithm; adaptive wormhole router; chip multiprocessor; flexible on-chip interconnection network; system-on-chip design; wormhole switching;

机译：多处理器互连网络；片上系统； 2D网格拓扑；自适应路由器架构；自适应路由算法；自适应虫洞路由器；芯片多处理器灵活的片上互连网络；片上系统设计；虫洞切换;

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1. An Analysis of On-Chip Interconnection Networks for Large-Scale Chip Multiprocessors [J] . DANIEL SANCHEZ, GEORGE MICHELOGIANNAKIS, CHRISTOS KOZYRAKIS ACM Transactions on Architecture and Code Optimization . 2010,第1期

机译：大型芯片多处理器的片上互连网络分析
2. An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures [J] . Antonio Flores, Juan L. Aragon, Manuel E. Acacio Journal of supercomputing . 2008,第3期

机译：平铺CMP架构的片上互连网络的能耗表征
3. Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip [J] . Pham P.-H., Song J., Park J., Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2013,第1期

机译：多处理器片上系统的片上置换网络的设计与实现
4. Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP) [C] . Seung Eun Lee, Jun Ho Bahn, Bagherzadeh N. International Symposium on Computer Architecture and High Performance Computing . 2007

机译：用于芯片多处理器的可行的片上互连网络（CMP）设计
5. Architecting on-chip interconnection network for future many-core chip-multiprocessors. [D] . Ouyang, Jin. 2012

机译：为未来的多核芯片多处理器设计芯片上互连网络。
6. On-chip constructive cell-network study (II): on-chip quasi-in vivo cardiac toxicity assay for ventricular tachycardia/fibrillation measurement using ring-shaped closed circuit microelectrode with lined-up cardiomyocyte cell network [O] . Fumimasa Nomura, Tomoyuki Kaneko, Akihiro Hattori, 2011

机译：片上建设性细胞网络研究（II）：使用环形闭路微电极和排成队的心肌细胞网络的片上准体内心脏毒性试验用于室性心动过速/颤动测量
7. Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP) [O] . Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh 2008

机译：芯片多处理器（CMP）可行的片上互连网络的设计

Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)

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