Improve Overlay Control and Scanner Utilization Through HighOrder Corrections

摘要

As the semiconductor industry continues to drive towards high volume production at the 50nm technology node and beyond, there are formidable barriers imposed not only from technical challenges but also from economic challenges related to controlling overlay tightly enough to meet the strict requirements of a increasingly smaller overlay control window. In this paper, the authors will show potential sources overlay error for a 50nm node process and detail a methodology to pinpoint the root cause and an application to help reduce these errors to facilitate the ramp of a new process technology for high volume DRAM/FLASH manufacturing. In short, based on a series of experiments and analysis, the authors have identified high-order wafer-level residual component to be the main contribution of the high residuals with the source attributed to the scanner mix-and-match set. In turn, an overlay control approach using high order correctables generated from the overlay metrology system and fed through the APC system will be able to effectively reduce the mix-and-match high residual errors.