An Asynchronous Divider Implementation

摘要

We present an asynchronous implementation of a novel division algorithm previously patented in [1]. Our implementation exploits the average-case behavior of the algorithm and uses the versatility of GasP circuits to implement the data-dependent latencies in the algorithm. On average, the delay per quotient bit for our implementation is 6.3 FO4 gate delays compared to 9.5 FO4 gate delays for a similar SRT divider implementation.