In this paper, we present a performance-oriented implementation flow for WCHB QDI asynchronous circuits aiming to be fully compatible with conventional EDA tools for synchronous designs. Starting from a simple standard-cell library for asynchronous logic, this flow builds pseudo-synchronous models of the cells. With these models, a simple set of pseudo-synchronous timing constraints can be given to industrial EDA tools to benefit from their optimization strategies, through all steps from synthesis to place & route. This flow was benchmarked against regular asynchronous implementation relying on maximum delay constraints. Pseudo-synchronous modeling allows achieving significantly better performance and regularity than asynchronous modeling, for faster run times and reduced design effort. The proposed flow was used for the physical implementation of a 20-node network-on-chip in the ST Microelectronics 65nm low-power technology. It achieves an end-to-end asynchronous throughput of 850Mflit/s in typical conditions, making it faster than all connected synchronous IPs.
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