THE HARDWARE IMPLENENTATION AND PERFORNANCE ANALYSIS OF AN ALL DIGITAL PHASE-LOCKED LOOP(ADPLL)

摘要

This paper describes the hardware implementation of a now type of all disitat phase-locked loop.analyses emphatically its all-kinds of performance,studies the stability of nonlinear quantization loop and deducts a new method of analysis the stability of nonlinear quantization loop.This PLL has some prominent characteristics,such as all disltal,high accuracy,tack of adjustment and multichanet disital output.Especially the loop's memory function,it would have an important practical value in extractins the bit synchronous signal in the data communication.