An Analysis of Digital Phase-locked Loops

摘要

This report focuses on second-order digital phase-locked loops (DPLLs) with uniformly sampled input, an amplitude-insensitive phase extractor and a conventional loop filter. Feedback to the number-controlled oscillator (NCO) consists of either phase rate, as in conventional loops, or both phase and phase rate. The phase/rate DPLL outperforms the rate-only DPLL by a substantial margin at high loop gain. Phase, including integer and fractional cycles, is computed in the tracking processor rather than by reading the NCO. This approach can provide accurate phase measurements even when NCO phase is discontinuously updated, as in the DPLL with phase and rate feedback. Other distinctive features include accurate timing and time-tag computation, and an averaging algorithm that produces phase values with output rate, noise bandwidth, and time tags that are independent of tracking loop parameters. Design emphasizes accuracy of output phase and improved performance at high loop gain. Loop analysis includes pole plots, curves for loop noise bandwidth, computation of maximum loop gain, plots of dynamic response, and derivation of the decorrelation interval for the noise on loop output phase. Phase accuracy can be improved in dynamic applications by computing measured phase as the sum of model phase and residual phase.