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Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper-Resistant AES on FPGA

机译:针对FPGA上的防篡改AES的LUT实现中的掩膜内双轨存储器

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In current countemneasure design trends against differentia] power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This paper describes our novel masked dual-rail pre-charged memory approach, called 'intra-masking dual-rail memory on LUT,' and its implementation on FPGA for tamper-resistant AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The design is independent of the ciyptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on FPGA showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced tamper-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.
机译:在当前针对微分功率分析(DPA)的共呼吸设计趋势中,除了安全算法之外,还需要门级的安全性。已经提出了几种双轨预充电逻辑(DPL)来实现这一目标。使用ASIC的设计由于其后端设计对布局和布线的限制而可以实现此目标。然而,由于在FPGA上的布局和布线方面存在限制的困难,因此在现场可编程门阵列(FPGA)上实现这些设计而又不泄漏信息仍然是一个问题。本文介绍了我们新颖的屏蔽双轨预充电存储器方法,称为“ LUT上的屏蔽内双轨存储器”,以及其在FPGA上的防篡改AES实现。在建议的设计中,所有不安全的节点(例如取消屏蔽和屏蔽)以及双轨存储器和总线都打包到单个LUT中。这使它们平衡且独立于布局和布线工具。该设计独立于密码算法,因此可以应用于可用的密码标准,例如DES或AES,以及将来的标准。它的实现不需要特殊的布局或路线约束。在FPGA上对1,000,000条AES实现的相关功率分析(CPA)攻击表明,机密信息受到了很好的保护,可以抵御一阶边信道攻击。即使在此实现中用于内存的LUT数量比常规的不受保护的单轨存储表查找AES的数量大七倍,并且比基于复合字段的实现的数量大三倍,但LUT的数量却更少比所有其他高级防篡改实现(如波形动态差分逻辑,屏蔽双轨预充电逻辑和阈值)高。

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