Design of the UTOPIA Interface of 10-Gigabit Ethernet with FPGA

摘要

Due to its low cost and packet data efficiency, Ethernet has now virtually dominated data transmission in Local Area Networks (LAN). Moreover, the 10-Gigabit Ethernet has begun to move Ethernet from the LAN out to encompass the metro area network. The technology features, protocol architecture and the frame format are introduced. In order to realize the logical boundary between the physical layer and the link layer, the protocol of UTOPIA (Universal Test & Operations PHY Interface for ATM) level4 is adopted. A method of realizing the UTOPIA interface of 10-Gigabit Ethernet is put forward and the function block diagram is presented. In order to reduce the power waste of the chip, the parallel algorithm is chosen in the design.