PROCESS MODELING PROCEDURE FOR VERIFICATION, VALIDATION AND TESTING PLANNING

摘要

Verification, validation, and testing (VVT) are the primary means of risk reduction in the product development process. Through systematic and early VVT strategy planning and continuous monitoring of the product development activities rework can be avoided and significant product lifecycle cost reductions can be achieved. In this paper a VVT process modeling procedure is described, which offers an effective method for reducing programmatic and technical risk through providing valuable assistance in the VVT strategy planning process. Programmatic risk reduction in the VVT process modeling procedure can be achieved by the elimination of redundant VVT activities, optimization of test schedule and restructuring of VVT activities into clusters based on the input needs of the tests and the deliveries of the product development activities. Through iterations in the VVT process during VVT strategy planning, the most effective combination of VVT activities can be found for the VVT goals and objectives. Iterations in the VVT process modeling procedure can be made based on the different durations, costs and effects on quality of the different VVT activities and methods applied at different points in the product lifecycle. Since the VVT strategy planning is an iterative process, the VVT process modeling procedure can be used to update the VVT process after every critical decision and milestone in the product development. The modeling concept for verification, validation and testing processes introduced in this paper, is currently being developed in a European research project, called SysTest (more information on the SysTest project can be found under: http: //www. secoe.org/0105.htm).