High-level model of sensor architecture for hardware and software design space exploration

摘要

For helping SoC designers to make right choices at the first development steps, we present here a new Hw/Sw high-level SoC model in order to facilitate the exploration. Because they offer a large optimization capacity, we particularly aim on operating system (OS) services, tasks mapping and some architectural parameters like frequency, supply voltage or data width. Simulation results provide consumption and time metrics and allow to verify our application functional validity. We focalize our work on a realistic mono-processor sensor architecture while aiming a future evolution to multi-processor and dynamically reconfigurable architecture. Our model is based on SystemC and allows very fast co-simulation including C++ tasks, OS and high-level models of the hardware architecture.