Estimation of Maximum Power Supply Noise in DSM Designs Including Parasitic Effects

摘要

Due to the continuous increase of the integration density and the clock frequency in VLSI designs, it become more important to estimate the noise of power supply networks efficiently and accurately. The parasitic effect should no longer be ignored in the noise analysis process. A genetic algorithm based method is presented to find the maximum power supply noise of some benchmark circuits including parasitic effects. In the work, the propagation delay and maximum envelope current is characterized as a function of its load capacitance and input signal transition time. The worst case voltage at a specified node is defined as the fitness value. And HSPICE is applied to compute the fitness value in GA. Experimental results show that the method reaches tighter lower bound, and is a good guide for further study.