Improvement of Data Retention Time using DRAM cell with Metallic Shield Embedded (MSE)-STI for 90nm Technology Node and beyond

摘要

As the technology node of DRAM goes below 100nm, the dimensional scaling of the devices greatly influences the major parameters that determine the performance of DRAM. Especially, the reduction of the isolation space in cell array can deteriorate the characteristics of cell transistor and storage node junction, which results in the degradation of data retention time. In order to overcome these issues, Metallic Shield Embedded (MSE)-STI has been proposed, but it has not been realized yet. In this paper, for the first time, we successfully demonstrate the DRAM cell transistor with MSE-STI for 90nm DRAM technology node and beyond. As a result, we can obtain the reliable cell transistor with low-doped channel profile, uniform threshold voltage distribution and low junction leakage current, and the most importantly we can greatly improve data retention characteristics.