DRAM CELL HAVING INCREASED DATA RETENTION TIME

摘要

A planar 4T-2C DRAM memory cell which balances leakage to a first order toincrease the data retention time is disclosed. The memory cell of the presentinvention usesMOS capacitors as load devices for a cross-coupled pair of pull-downtransistors, instead ofTFT transistors, pmos transistors or high resistive poly which have been usedin similarcircuits of the prior art. More specifically, the tunnelling current throughthe thin gate oxideof the MOS capacitors is used as the load for the cross-coupled devices. Thecross-coupledtransistors and the access transistors have thicker gate oxides in order tominimize theirleakage. The resulting layout of the memory cell of the present invention hasa 30 percentsmaller area than the area of a conventional 6T SRAM memory cell. Dataretention time inthe memory cell of the present invention is about 10 times longer thanprevious 4T DRAMcells.