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Enhanced retention time for embedded dynamic random access memory (DRAM)
Enhanced retention time for embedded dynamic random access memory (DRAM)
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机译:延长了嵌入式动态随机存取存储器(DRAM)的保留时间
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摘要
Increasing the retention time of an embedded dynamic random access memory (DRAM) is disclosed. An embedded DRAM includes a metal oxide semiconductor (MOS) capacitor. The capacitor has a storage node formed between a P+ doped region and a polysilicon plate within an N well. An N− doped region is situated substantially completely under the polysilicon plate and substantially under the P+ doped region. The presence of the N− doped region decreases the threshold voltage of the capacitor and reduces effectively the junction leakage current to the N well, achieving a larger retention time.
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