Dynamic logic synthesis

摘要

A self-timed dynamic logic family, clock-delayed (CD) domino, wasndeveloped to provide non-dual-rail gates with inverting or non-invertingnoutputs. CD domino circuits are as easy to synthesize as static circuitsnand synthesis tools developed for static CMOS are used as part of anmethodology for automating the design and synthesis of dynamic circuits.nThe methodology and CD domino's characteristics are demonstrated in thensynthesis of five MCNC combinational logic benchmark circuits.nSimulations of extracted chip layouts for the circuits show speednimprovement factors of 2.17 to 6.28 compared to their static CMOSncounterparts