Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology

摘要

A power efficient charge pump is proposed. The use of low voltage transistors and of a simple 2-phase clocking scheme allows the use of higher frequencies compared to conventional solutions, thus obtaining high current, high efficiency and small area. Measurements show good results for frequencies around 100MHz. Two testpatterns have been fabricated, one with three stages and one with five stages, in a 1.8V 0.18μm standard CMOS digital process (6 metals) with triple well. High voltage capacitors have been implemented using metal to metal parasitic capacitance.